1. Technical Field
The present invention relates to on-chip diagnostics and testability, and in particular, to phase-locked loop circuits with jitter measurement.
2. Description of the Related Art
As technology advances, predicting the behavior of transistor devices and passive elements such as resistors and capacitors becomes increasingly difficult. Increased uncertainty in the modeling of these devices sometimes mandates integrated circuit designs to function beyond original targets in order to provide enough performance margin over process, voltage, and temperature (PVT) variations. Conservative designs may often result in more power and area consumption than is needed.
If internal system parameters can be measured and used to adjust the system parameters, the system design margin can be greatly enhanced. In the past, system diagnostics were performed by measuring available off-chip test nodes. However, an external diagnostic path is slow, and solutions are not always found. Furthermore, the limited off-chip visibility of internal analog/digital waveforms results in limited learning rates for yield. Hence, the demand for on-chip testability and diagnostics has greatly increased.
In phase-locked loop (PLL) design, key PLL parameters such as jitter, static phase error, and control voltage range are extremely difficult to evaluate in integrated systems. Among these, measuring jitter performance is very challenging, as timing uncertainty in clock generation increases with modern technology.